The present invention relates generally to computer systems having open architecture buses. More particularly, the present invention relates to compensating for the insertion or removal of additional random access memory devices in a computer system. More particularly still, the invention relates to adjusting clock skew to compensate for the electrical characteristic changes associated with the insertion or removal of random access memory devices.
Computers represent information in a binary format. That is, computers represent information in variables that have only two states, otherwise known as digital variables. In the electrical context, the two states of information are generally represented by two voltages—a low voltage (or no voltage) representing a first state and a high voltage representing a second state. In some systems, a low or zero voltage state represents a logic zero, and a 3.3 volt state represents a logic one. Computers perform their amazing tasks and talents by operating on and manipulating strings of information represented by these zeros and ones.
Each portion of a computer system is designed to perform a particular task. To complete the operations required for the overall execution of a program, for example, information must be transferred between various portions of the computer system. The microprocessor of the computer system is the device charged with performing most operations on data within the system to perform tasks. However, a microprocessor is limited in its data storage capacity, and thus computer systems also have memory devices that store information for the microprocessor and other computer system components. At various times in the operation of the computer, the microprocessor requests copies of information stored in the main memory, and likewise requests the placement of information back into that main memory for semi-long-term storage. As computer microprocessor speeds increase, the transfer of information between the various components of the computer system becomes more complicated. One of the complicating factors in this exchange of information is how fast the voltages representing the logic states zero and one can be forced upon or driven to buses within the system.
Consider, for example, two generic devices within a computer system coupled by a bus system consisting of a plurality of wires or traces on a printed circuit board 64 bits wide. Considering only the data lines, and not the address or error correction lines, there would be 64 wires or traces on the printed circuit board coupling the first generic device, from which information is transferred, to the second generic device, to which the information is transferred. At particular pre-defined times based on a host clock signal, the voltage on each trace of the bus connection represents a logic zero or a logic one as described above. The sending device drives those voltages, and the receiving device senses those voltages, hence an exchange of data. If more than 64 bits of information need to be transferred, then the data bus operates multiple times, adjusting the voltages on each trace to represent the corresponding logic value for that particular portion of the data transfer.
FIG. 1 shows an idealized exemplary voltage on one of those data bus traces as a function of time. In particular, FIG. 1 shows that initially the voltage on that trace line to be low or zero, which could represent a point in time where no information exists or is being driven. Instantaneously, the voltage rises to a higher voltage level, representing a first logic state. As time passes, the high voltage again instantaneously changes to a lower voltage, representing the second logic state. The drawing of FIG. 1 is said to be idealized because no actual electrical system is capable of generating a waveform having the instantaneous changes in voltage shown. Stated another way, no physical system is capable of producing a waveform with such sharp transitions in voltage.
FIG. 2, by contrast, shows a more realistic transition in logic states between a low voltage and a high voltage of the exemplary trace of the data bus under consideration. FIG. 2 shows that rather than an instantaneous change in voltage, the voltage slowly, and to a great extent exponentially, rises until at some point it reaches the higher voltage state. Likewise, FIG. 2 shows that the transition from a high voltage to a low voltage is not instantaneous in actual physical systems, but instead decays exponentially toward the lower voltage point.
These deviations in waveforms between FIG. 1, in the idealized case, and FIG. 2 are attributable to parasitic capacitances inherent in any electrical system. How fast, or how slow, a change of state may occur is proportional to the parasitic, or designed, capacitance attached to the bus system. Whether or not the slow rise and fall times for a particular waveform are a problem depends on the speed at which information is exchanged.
Early computer systems had microprocessors that operated in the low tens of megahertz (MHz) range. In the late 1980s, for example, a computer system with a microprocessor operating at 12 MHz was considered extremely fast. By contrast, within the last few months of the filing date of this patent, some computer manufacturers have offered computer systems with microprocessors that operate at 1 GHz (1,000 MHz) or more. FIG. 3 shows an exemplary plot as a function of time of the voltage of a clock signal operating at 12 MHz. More specifically, FIG. 3 shows one complete cycle of a 12 MHz clock signal that begins at point A and ends at point B. The period of a 12 MHz clock, that is the amount of time to complete one cycle, is about 83 nano-seconds (ns). Thus, the time represented on the horizontal axis of the plot between point A and point B likewise represents 83 ns. Comparing FIG. 2 plotted directly above FIG. 3, it is seen that although there is a certain amount of time required for the signal represented in FIG. 2 to hit its maximum voltage, this time is well within the first half clock period of the 12 MHz clock.
By contrast, FIG. 4 shows the plot of one complete cycle of a 133 MHz clock, which speed is the standard operational speed of data transfer across buses using current technology. The time axis of FIG. 4 is the same as that of FIG. 3. The period of the waveform of a 133 MHz clock is about 7.5 ns, which, by referring to FIG. 3, is significantly shorter than the period of a 12 MHz clock. In a system having a bus transfer scheme operating at 133 MHz, a rise time as slow as that indicated in FIG. 2 causes significant problems in the transfer of information. Indeed, the waveform plotted at FIG. 2 would not even reach its maximum value before the completion of a complete waveform of the 133 MHz clock. Given that most exchanges of information happen on a rising or a falling edge of the clock signal, it is apparent that a computer system having a parasitic capacitance resulting in a waveform of that of FIG. 2 would not be capable of transferring information even on the rising edges only of a 133 MHz clock, as it would take more than one complete period for the voltage to develop on the trace of the data bus.
Computer manufacturers have been somewhat successful in managing this parasitic capacitance to keep it at a level below which causes problems as the speed of data transfers have increased. However, open architecture systems give the end user the capability of modifying the components of their systems. Each time the end user adds a component to the system, that user also adds parasitic capacitance, which affects the data transfer capability in the system.
Thus, what is needed is a way to adaptively compensate for the parasitic capacitance of a computer system.